acmpesuecc / aes-128-sysverilog-riscv

AES-128 block written in SystemVerilog
MIT License
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Testbench required for shift_row.sv #9

Open skudlur opened 11 months ago

skudlur commented 11 months ago

Description

Add a testbench for shift_row.sv to validate it's functionality. Please refer to this for a tutorial on writing a testbench.

Notes:

vandanaj0110 commented 11 months ago

Can you please assign me to this?

skudlur commented 11 months ago

@vandanaj0110 assigned

ssether04 commented 11 months ago

can i get assigned if this is still open?

vandanaj0110 commented 11 months ago

@skudlur I have a doubt..could you come to sem hall 1

vandanaj0110 commented 11 months ago

@skudlur Could you come to sem hall 1