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acsl-technion / nica

An infrastructure for inline acceleration of network applications
BSD 2-Clause "Simplified" License
30 stars 13 forks source link

interconnection between CPU & FPGA #1

Closed Winters123 closed 5 years ago

Winters123 commented 5 years ago

Really good work. Just would like to know if the packets traveling between CPU and FPGA has the metadata in the front? If so, how does the pkt go through ASIC nic between the two?

haggaie commented 5 years ago

Thanks. There are two different modes of operation for transferring packets between the FPGA and the CPU in NICA.

For UDP packets, NICA itself does not add metadata, and the ASIC NIC steers packets based on the UDP headers to the user-space network stack (VMA).

For the custom ring, NICA communicates using the RoCE UC protocol with the ASIC NIC, so it adds the RoCE BTH header. The ASIC NIC uses the metadata in the BTH (QP number) to steer the packet.

Winters123 commented 5 years ago

Got it. :)