Some M4-specific timing adjustments to help this work with both old and new matrices. Across all F_CPU settings, aims for 20 MHz throughput with 50% duty cycle on CLK (for the unrolled parts of the "blast" loop -- every Nth pulse will diverge from that a bit). Tested on logic analyzer and on six distinct varieties of 64x32 matrix.
Additionally: a fix for small-chunk-long-chains and some comments and README notes on dealing with NOPs in the future.
Some M4-specific timing adjustments to help this work with both old and new matrices. Across all F_CPU settings, aims for 20 MHz throughput with 50% duty cycle on CLK (for the unrolled parts of the "blast" loop -- every Nth pulse will diverge from that a bit). Tested on logic analyzer and on six distinct varieties of 64x32 matrix. Additionally: a fix for small-chunk-long-chains and some comments and README notes on dealing with NOPs in the future.