Closed TobleMiner closed 3 years ago
According to the second diagram on page 52 and various implementations of SSD1306 interfaces the CPOL seems to be irrelevant. Thus I'm closing this PR for now. Please feel free to reopen if you are having issues with mode 0.
Previously the SPI was operated in mode 0. However the 4-wire serial timing diagrams in the SSD1306 datasheet show that CPOL must be 1, because clock is high at idle (page 52). This commit changes the SPI to operate in mode 3 where CPOL is 1, placing the clock in high state when idle.
Datasheet: https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf
Relevant diagram:
As far as i'm aware this should not break compatibility with any SSD1306 based displays. Due to the seemingly large amount of SSD1306 clones I'd appreciate third party testing. Especially since I do not have a single display to test this change on at the moment. I did only notice the disparity between spec and implementation while developing a SSD1306 emulator, looking at logic analyzer captures.