The datasheet states
"The DREQ pin/signal is used to signal if VS1053b’s 2048-byte FIFO is capable of receiving data. If
DREQ is high, VS1053b can take at least 32 bytes of SDI data or one SCI command. DREQ is turned
low when the stream buffer is too full and for the duration of a SCI command." which means DREQ has to be checked before sending sci commands to the VS1053. This library failed to do so which might cause some unpredictable behavior.
For the ESP8266 the watchdog is fed (yield() was not sufficient in my tests), while waiting for DREQ.
The datasheet states "The DREQ pin/signal is used to signal if VS1053b’s 2048-byte FIFO is capable of receiving data. If DREQ is high, VS1053b can take at least 32 bytes of SDI data or one SCI command. DREQ is turned low when the stream buffer is too full and for the duration of a SCI command." which means DREQ has to be checked before sending sci commands to the VS1053. This library failed to do so which might cause some unpredictable behavior. For the ESP8266 the watchdog is fed (yield() was not sufficient in my tests), while waiting for DREQ.