Closed richbai90 closed 2 years ago
the feather examples are tested to work with the m4 feather as long as wiring follows the tutorial
Hello Ladyada, I really apprecaite you getting back so quickly. I'm not sure what I am missing then. I've triple checked my wiring, here's how I have it setup
MISO, MOSI, and SCK all go from the labeled pins on the radio to the center SPI pins on the Grand Central. NSS goes from the radio to digital pin 53, with a 100K PU resistor in parallel. The radio is fed from the 3v3 output on the Grand Central and a 10uF electrolytic capacitor is in parallel with ground to filter noise. I have tripple checked the polarity of the capacitor also, given that it's electrolytic. I'm using the GC as the TX device, you can see my code in the original issue was adapted from the raw TX Feather example, and the Feather 32u4 RFM69HCW board as the receiver running the raw RX Feather example.
hiya, questions about how to use adafruit products are best posted in the adafruit forums at forums.adafruit.com thanks! :)
Understood, I'll take this matter up over there. Thank you!
I'm trying to use your library to drive an RFM69HCW radio module via SPI. The problem is that the board never gets out of the
waitSendPacket
loop. By printing out the values of theRegIrqFlags1
andRegIrqFlags2
registers as well as printing some debug lines in thesend
method I've been able to track the issue down to this flow:waitSendPacket
It is strange that
PLLLock
should be set when the Mode according to the library is IDLE. Per the datasheet that's not actually possible. So the question becomes, why is the mode stuck in IDLE even when the Radio is reporting that this isn't the case. My code is adapted from the example code written for the feather32u4, which you can see below.Some Other Details
I've connected the radio in the recommended way, with a pull up resistor in parallel with
NSS
and a filtering capacitor in parallel with power and ground to short competing AC signals.My initial thought was that the 120MHz clock was way too fast (the library seems to expect 16MHz tops) but upon closer inspection the SPI is setup to be 4MHz by default and after division by the library this becomes 1MHz, well within the 10MHz limit. I've confirmed this with a logic analyzer connected to SCK (See the image beneath the code)
I've tried to do as much of the leg work as possible so hopefully this is a relatively simple thing that I am missing. Thank you in advance.