Is it allowed to assign a scalar value to an unpacked array?

[YaoYang357]

I found that in the reset logic of the controller.sv module, the assignment to the register array is done using a scalar value. However, this results in an error during compilation with Quartus II 18.1. So I rewrote the code in the following form:

always @(posedge clk) begin
        if (reset) begin 
            mem_read_valid <= 0;
            mem_read_address <= {`NUM_CHANNELS{`ADDR_BITS'd0}};

            mem_write_valid <= 0;
            mem_write_address <= {`NUM_CHANNELS{`ADDR_BITS'd0}};
            mem_write_data <= {`NUM_CHANNELS{`DATA_BITS'd0}};

            consumer_read_ready <= 0;
            consumer_read_data <= {`NUM_CHANNELS{`DATA_BITS'd0}};
            consumer_write_ready <= 0;

            current_consumer <= {`NUM_CHANNELS{`CONSUMER_INDEX_WIDTH'd0}}; // parameter CONSUMER_INDEX_WIDTH = $clog2(NUM_CONSUMERS)
            controller_state <= {`NUM_CHANNELS{3'd0}};

            channel_serving_consumer = 0;
        end else begin 
               …

Is this the correct approach? At least it no longer produces an error.

By the way, I converted the SV file to a V file (and made adjustments to fit V), but it seems like learning SV through this project would be a good choice. What are the advantages of using SV for this project?

[adviyer]

I am pretty sure SystemVerilog extends '0 to match the bitwidth of the vector it's being assigned to (See https://verificationacademy.com/forums/t/extend-value-to-vector-size-in-sv/33021).

I couldn't find any official documentation on assigning multi-bit registers to '0', but I think multi-bit registers being assigned using this syntax should throw an error (see page 11 of this document: https://lcdm-eng.com/papers/snug13_SNUG-SV-2013_Synthesizable-SystemVerilog_paper.pdf)

The above document also illustrates the advantages of SystemVerilog and compares it to Verilog.

Also, wrt this project, assignments such as

mem_read_valid <= 0;
mem_read_address <= '0;

should ensure all bits are set to 0 without compile errors. Let me know if that works!