VCS Compile Issue - Githubissues

PauloCarvalhoSP commented 2 weeks ago

Hi,

I did try run a simulation using the following command:

make vcscomp sim USE_SIMULATOR=vcs WAVES=fsdb

But I had the following compile error:

Parsing design file '../master_agent/apb_uvc_master_pkg.sv'

Error-[SE] Syntax error Following verilog source has syntax error : "../master_agent/apb_uvc_master_pkg.sv", 16: token is ';' package apb_uvc_master_pkg;

I'm using Synopsys VCS V-2023.12-SP2

Is there any missing argument into the command line or in the Makefile?

Thanks,

Paulo

neelpambhar10 commented 2 weeks ago

Hi

Are you integrate this vip into your environment ?

adit0131 commented 2 weeks ago

Yes it was integrated into my environment.

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From: neelpambhar10 @.> Sent: Wednesday, September 25, 2024 5:42:17 PM To: adit0131/APB_VIP @.> Cc: Subscribed @.***> Subject: Re: [adit0131/APB_VIP] VCS Compile Issue (Issue #1)

Hi

Are you integrate this vip into your environment ?

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PauloCarvalhoSP commented 2 weeks ago

Yes, I'm trying to run first a test from your VIP using your makefile from run folder.

PauloCarvalhoSP commented 2 weeks ago

The issue reported here is using the Makefile available inside the run folder of this VIP.

adit0131 / APB_VIP

VCS Compile Issue #1