First of all, thank you for your efforts on automating AMBA interconnect generation.
One minor thing about the AHB generation is that you're using "priority" as a function name in the AHB module. However, priority is a reserved work in SystemVerilog. Therefore, when I compile the design with systemverilog option on, the compiler reports a syntax error.
Dear professor Ki,
First of all, thank you for your efforts on automating AMBA interconnect generation.
One minor thing about the AHB generation is that you're using "priority" as a function name in the AHB module. However, priority is a reserved work in SystemVerilog. Therefore, when I compile the design with systemverilog option on, the compiler reports a syntax error.
It will be appreciated if you fix the issue.