SNAPPY2020

[ChiemseeNL]

Hello Adrian, this is a great new release/upgrade. I was wondering when you will release your SNAPPY2020 cartridge shown by Robin on youtube? Or is there some place we can see the progress? Many thanks for all the hard work!

[gillham]

Adrian mentioned on Twitter that some FPGA parts are not available so it is more or less on hold until there is availability.

[adrianglz64]

Sorry, meant to reply to this sooner. Unfortunately, @gillham is right. At least two of the chips I used in the design are currently unavailable due to chip shortages and/or supply chain issues. I actually picked a CPLD that's in the same family as the one used in the EF3 because it would make the design simpler (it's 5V-tolerant). It was not an inexpensive chip to begin with, and now it just about tripled in price and is not in stock anyway.

I do want to try making another small batch of prototypes with some design changes (assuming I can find the chips.) In the meantime, the ROM still needs quite a bit of work, so I'll continue to focus on that.

[MrAureliusR]

@adrianglz64 Instead of using a CPLD, it might be worth grabbing one of the less expensive, widely available FPGAs (like the Lattice iCE40 or MachXO2, or even one of the older, cheap Xilinx parts like a Spartan-6) and just adding level translators where needed. Level translation is pretty easy to do with chips like the TXS0108E. It might increase the BOM cost a bit, but at least they are available and will remain available for the foreseeable future. The 5V tolerant CPLDs are pretty much gone, most manufacturers have discontinued all their parts, or have Last Time Buy dates coming up. It's unfortunate for those of us who mix modern designs with vintage computers (something I do quite a bit!) but at least there are reliable ways to solve it.

I don't know if you're planning on releasing the HDL you have for the prototype, but if you do I'd be happy to take a look at it and try to re-work it to fit into a modern small FPGA. I particularly like the Lattice iCE40 range as you can get them in pretty small sizes, they're inexpensive, the toolchain is easy to use, and they are usually in stock by the boatload at most suppliers.

[adrianglz64]

It definitely seems like using a 5V-tolerant CPLD is no longer an option. They weren't cheap to begin with, and for a while they were out of stock everywhere. They do seem to be available again, but now they're ridiculously overpriced. I chose a Xilinx CPLD (XC95288XL) so I could first tackle getting DMA working without having to worry about level translation (yet), as I had never done a DMA-capable cartridge before. I didn't think I was even going to be able to fit all of the REU's functionality on that chip, let alone adding Super Snapshot V5 to it.

I do plan on releasing the HDL and the PCB design, but the source needs some work as it's kind of a mess right now. The original plan was to release the CPLD-based design and then move on to an FPGA for the next iteration. I was originally looking at FPGA/CPLD families like the Altera/Intel max10 that have built-in configuration memory and are available in single 3.3v supply options, but it those are also fairly expensive now (except for maybe the smallest 2K LE part). The iCE40 family looks interesting (and affordable), but it requires a 1.2V core supply in addition to the I/O supply (3.3V)?

In any case, I'm definitely open to suggestions. I've been dragging my feet on this for a bit too long now.

[MrAureliusR]

The iCE40 do require 1.2 core voltage, but if you check out their reference designs, they use an expensive part called the LT3030 that is an ultra low dropout dual regulator that generates both 1.2V and 3.3V from 5VUSB. However, there's nothing magic about it, and you could just as easily use a couple of the ultra cheap standard linear regs.

In particular the iCE40 LP/HX series is quite nice. Pretty much all Lattice parts have built-in config flash, one of the reasons people like their parts. That and I believe there's an entirely open toolchain for them. They're typically less expensive than Altera/Xilinx parts and they make parts in packages that are actually hand-solderable, like QFP-144 etc. Even so, the smaller parts are BGA but I find BGA easier to work with than, say, WLCSP or any of the other really tiny packages.

If you scroll down to the end of the iCEstick guide they have a full reference design schematic which is worth checking out: https://www.latticesemi.com/view_document?document_id=50701 EDIT: Huh, it looks like that part does have an external SPI flash. I wonder if all the iCE40 parts are like that? I was under the impression that they had the same built-in flash like the XO2/XO3 parts... that was one of Lattice's big selling points.

[adrianglz64]

Unfortunately, it looks like the built-in config memory in the iCE40 family is OTP. From iCE40 Programming and Configuration:

The iCE40 LP, iCE40 HX, iCE40 Ultra™, iCE40 UltraLite™, and iCE40 UltraPlus™ devices also have an on-chip, one-time programmable NVCM (Non-Volatile Configuration Memory) to store configuration data

I guess that would explain why that iCE Stick evaluation board has SPI flash.

Either way, I'd love to continue discussing migrating the design to a modern FPGA if you're interested, but doing it on github issue comments is probably not the best way. Email/discord/slack would work, but I guess there isn't a way to send a private message on here?

[MrAureliusR]

That's okay, my Discord username is the exact same as my username here. Feel free to add me! :)

[adrianglz64]

Oops.. discord says you're not accepting friend requests! Mind unblocking that for a bit? I think you can only DM someone you're not friends with if you're on the same server.

[MrAureliusR]

Oops, temporarily opened up.