When capturing frames, the first cycle is always an error. I suspect it is an issue related to the timing of integration vs frame readout. Possible solutions:
Correct the VHDL code to do integration first like it should
Modify Nios code to ignore the first #cycles of frames. This is a nice solution for ignoring the first X frames after a reset that often have slightly different precision as the system 'settles'.
When capturing frames, the first cycle is always an error. I suspect it is an issue related to the timing of integration vs frame readout. Possible solutions: