Transform INBOX into a FIFO

[adumont]

That will allow us to plug a UART-RX to the FIFO.

Also modify the CPU FSM so that when in state DECODE, when Instr=INBOX & empty=1 , next_state <= DECODE (that is: stay in the same state until something arrives in INBOX)

[eine]

You mind find these references useful:

• https://github.com/VUnit/vunit/blob/master/examples/vhdl/array_axis_vcs/src/fifo.vhd#L80-L82
• https://github.com/VUnit/vunit/blob/master/examples/vhdl/array_axis_vcs/src/axis_buffer.vhd

[adumont]

Related discussion in #FPGAwars groups at https://groups.google.com/d/msg/fpga-wars-explorando-el-lado-libre/f8mjYT8JR5k/c-YnNGiPAAAJ .

[adumont]

"Also modify the CPU FSM so that when in state DECODE, when Instr=INBOX & empty=1 , next_state <= DECODE (that is: stay in the same state until something arrives in INBOX)"

--> That part was done in cf450b8fa02cfb57a90b57e8325119aad9afeec1. Limitation in Logisim forces me to add new state WAIT_INBOX instead of stay in DECODE until empty=0. Review in #7.

[adumont]

See https://github.com/adumont/uartrx-fifo/ for a working FIFO example that could be used for INBOX.

[adumont]

Done in e28dc764246d5af42a15573c7af151057fdb22d8