Consider using icebram to change MEM/PROG per level in .pnr file at synthesis time

[adumont]

https://stackoverflow.com/questions/36852808/modify-ice40-bitstream-to-load-new-block-ram-content

that would modify the workflow:

icebram --> random mem_fake.hex & prog_fake.hex files (will be replaced later) [only once, stored in source?]

for each board, but common for all level: yosys .v --> .bliff arachne-pnr lif --> board_generic.pnr

for each level: icebram memfake.hex mem[level].hex < board_generic.pnr > tmp.pnr icebram progfake.hex mem[level].hex < tmp.pnr > board_level.pnr icepack board_level.pnr --> board_level.bin

It's basically a change in the /verilog/Makefile .