Not marking ControlUnit.state as FSM state register: Register has an initialization value.

[adumont]

yosys> fsm_detect

5. Executing FSM_DETECT pass (finding FSMs in design). Not marking ControlUnit.state as FSM state register: Register has an initialization value.

So that seems to imply that it's wrong to set a initialization value to the state register.

As a reference, it's true that Cummings papers don't show any init. value in the examples. http://www.sunburst-design.com/papers/CummingsSNUG2003SJ_SystemVerilogFSM.pdf

Full script: yosys> read_verilog ControlUnit.v proc; opt; fsm -nomap fsm_detect fsm_extract fsm_info fsm_export -o ControlUnit.kiss2

BTW, we can draw the kiss2 file using graphviz, see https://stackoverflow.com/questions/32645965/fsm-export-using-yosys

[adumont]

Fixed in 39ace17.