Closed adumont closed 5 years ago
Can be achieved by:
diff --git a/verilog/ControlUnit.v b/verilog/ControlUnit.v
index a182a12..38c0678 100644
--- a/verilog/ControlUnit.v
+++ b/verilog/ControlUnit.v
@@ -104,9 +104,9 @@ module ControlUnit (
endcase
S_COPYFROM : nextstate = S_Inc_PC;
S_DECODE : case (opcode)
- o_INBOX : if( inEmpty ) nextstate = S_WAIT_INBOX;
+ o_INBOX : if( inEmpty ) nextstate = S_DECODE;
else nextstate = S_INBOX;
- o_OUTBOX : if( outFull ) nextstate = S_WAIT_OUTBOX;
+ o_OUTBOX : if( outFull ) nextstate = S_DECODE;
else nextstate = S_OUTBOX;
o_HALT : nextstate = S_HALT;
default : nextstate = S_INCPC2;
(passes all tests OK).
ALthough now I'm not really sure it's usefull. Sure it's less states, but it's easier to keep it for consistency with the Logisim FSM design...
Implemented in f941c8b
Limitation in Logisim FSM, doesnt allow to stay in same state (wait here).
Review when implementing with Fizzim / Verilog.
In DECODE state, When ( Instr = INBOX AND empty = 1 ), FSM should stay in DECODE (until empty = 0).
For now I have added the extra step WAIT_INBOX to transition back back to DECODE, to reevaluate again.
Doesn't seem very eficient.