aesim-tech / simba-project

Roadmap & issue tracking
7 stars 0 forks source link

Error when parsing design variables of a subcircuit #374

Open guillaumefontes opened 9 months ago

guillaumefontes commented 9 months ago

If a design variable is created in the panel of the "opened" subcircuit as described belo:

image

It gives the following error:

image

No error thrown in the variable is defined in other design variable spaces (top level and mask level).

test_design_variables.zip