investigate & implement FPU_IRQHandler

[adam-at-epsilon]

Since we're doing the PID controller in hardware FPU, it could be a good idea to implement the FPU_IRQHandler.

It should be possible to get divide by zero, overflow and underflow exceptions.

[adam-at-epsilon]

ARM has a useful page on floating-point in Cortex M4

http://community.arm.com/docs/DOC-7544

[adam-at-epsilon]

an example

http://visualgdb.com/tutorials/arm/stm32/fpu/

[adam-at-epsilon]

look here for the address of the FPSCR register which holds the overflow & underflow status bits

This is available among the registers from the debugger, creating an infinte loop like so:

    float fl = 2;
    while (1) {
      fl = fl * 2;
    }

Shows the content of the fpscr register to be 0x14 which precisely matches the documentaiton.

The remaining question is why an interrupt is not generated/detected by HAL.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABGHFIB.html

[adam-at-epsilon]

Checking the NVIC->IABR register with the debugger show all IABR[0-7] to be zero even though fpscr register says 0x14 so my working theory is that the interrupt was not enabled correctly.

[adam-at-epsilon]

Try using NVIC_GetActive for a periodic check as a work-around.