Open phatina opened 6 years ago
I have the exact same issue. Did you manage to solve this on your own ?
Compilation is successful, flashing looks successful too, but the CHIP is stuck in FEL mode (I can reflash it without having to plug the jumper-cable).
I used a FTDI to monitor the serial port, but with no success, no output when I plug the power on after flashing it (Although I can see output when I flash the device)
I also tried to compile images with the following branches
But the compilation fails.
Thanks in advance
Hi, no luck so far.
Description Having built an image using your layer meta-chip, I can flash CHIP, but after successful flashing, it remains in FEL mode every time I power it on.
Steps to reproduce the issue:
Describe the results you received: Device is always in FEL mode with or without jumper wire between FEL pin and ground.
Describe the results you expected: Normal boot.
Additional details (revisions used, host distro, etc.): I built the image on Fedora 25.