External timing model

[wujw20]

Recently, I am using the riscv-vp in my project. I want to consult that how can I find the file riscv-timing-sim.so and riscv-timing-db.xml mentioned in timing_external.h?

std::string RISCV_TIMING_SIM_LIB = "riscv-timing-sim.so"; std::string RISCV_TIMING_DB = "riscv-timing-db.xml";

Thanks a lot!

[dyazzvlue]

Same question. Is there any document or tutorial? Thanks !

[Cirromulus]

Hi! These files were generated by the Uni Tübingen (EKUT) in a cooperation. We can't provide these files, as the generation is proprietary to the embedded systems faculty at the EKUT.

[cnjsdfcy]

Just finished reading the paper of your timing model, what a pity than we can't read and learn the code implementation(꒦_꒦) .

[Cirromulus]

The paper you referenced does not use the external timing model, but instead uses the branch prediction and cache model of the branch https://github.com/agra-uni-bremen/riscv-vp/tree/hifive1-core-timing-model. It is based on an older version of the VP, but if there is enough interest, there can be done some work to merge it into master.

[cnjsdfcy]

Great! Thanks for the information. BTW, any update or newly published paper on your research about cycle-accurate DBT methods as listed in above paper's future work ?

[cnjsdfcy]

The paper you referenced does not use the external timing model, but instead uses the branch prediction and cache model of the branch https://github.com/agra-uni-bremen/riscv-vp/tree/hifive1-core-timing-model. It is based on an older version of the VP, but if there is enough interest, there can be done some work to merge it into master.

Hi, As you mentioned, could you please merge the hifive1-core-timing-model into master branch, after that there will be a unified timing model interface for both the example hifive1 and your internal timing library. Also, we can follow your newest master branch instead of older hifive1 branch.

Thanks~