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aignacio / ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
MIT License
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Implementation on an FPGA #16

Closed kutaybulun closed 4 months ago

kutaybulun commented 4 months ago

Hello! I want to synthesize this project on an FPGA in Vivado to do research on and understand the behaviour of NoC's , is there any guide that i can follow to do this? Or is it possible to synthesize this project on an FPGA at all? Thank you for your hardwork on this project!

aignacio commented 4 months ago

Hey @kutaybulun, you can take the RTL, configure it as you want, and embed it into your flow, as a reference, see how it was done here: https://github.com/aignacio/mpsoc_example