Does the router use a pipeline structure?

[Alexander-0619]

Hi!

It seems that the router does not employ a pipeline structure. Do you consider that a pipeline structure is conducive to system realization? I also wonder whether the virtual channels in the router have to receive an entire packet before accepting the flit data of another packet?

[aignacio]

@Alexander-0619,

I had plans to include a generate of skid buffers but didn't have time to implement yet. Also, the vcs will preempt the higher priority flits whenever they appear. I'm sick atm but I'll keep track on adding the skid buffers.

Tasks before closing the issue:

• [ ] Include generate for skid buffers

[Alexander-0619]

Thanks for the update and hope you get well soon.

[Alexander-0619]

Hi! @aignacio

I originally wanted to use the skid buffer to connect the input module and output module inside the router because both modules apply the valid-ready mechanism. However, the ready_i signal of input module is actually affected by the data_o and valid_o of input module . However, for TX applicable to skid buffer, ready_i and valid_o are independent as follow. So skid buffer can only be used to connect input modules and output modules of different routers?

[aignacio]

Hey @Alexander-0619,

I still didn't have time to evaluate this, but if I believe the best approach here in my opinion would be to include the skid buffer at the output module (in the generate statements) with parameter set to REG_OUTPUT == 1. This way you break entirely the combinatorial path logic and improve timing. Meanwhile, if you are having timing issues, I suggest isolating the NoC in its own floorplanning and connecting the AXI slaves through this design here. This basically adds slice registers (skid buffer) into the AXI path that should help with timing closure.

[Alexander-0619]

Thanks for your advice. I'll try, by the way, how to run tb of this design?

[aignacio]

Hey @Alexander-0619, take a look at the instructions here for instance.

[Alexander-0619]

I see. Thx!