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alanbarr / STM32F4_Streaming_Mic

STM32F407 Internet Streaming Microphone
https://www.theunterminatedstring.com/tag/project_stm32_streaming_mic/
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Help with PDM to PCM in STM32F407 #1

Closed j054n closed 5 years ago

j054n commented 6 years ago

Hi Mr. Barr, I have reading your post "Probing PDM: MP45DT02 and STM32F407" and looking in the code, to try using a similar filter than yours in this platform for sampling at 96KHz a modulated signal on a carrier of 16KHz, I can not obtain good results, I dont know if it's not posible or I'm using bad filter parameters cutoff freqs, .... Do you have any suggest or any example that i could help me with my purpose? Thanks in advance.

Josan

alanbarr commented 6 years ago

Its been that long since I've looked at this I don't think I remember much that wasn't documented in that blog post.

Are you suggesting that your I2S clock is set to 96 kHz, or is that the desired frequency post filter? If the former, the MP45DT02 needs to be clocked between 1 MHz and 3.25 MHz.

Have you tried using ST's libPDMFilter? See their application note: "AN3998 - PDM audio software decoding on STM32 microcontrollers". From memory it wasn't too hard to get up and running. I would suggest trying their demo configuration initially just so you can start from a working point.

j054n commented 6 years ago

Thank you for the response and your suggestion, I have yet tried with ST demo and libPDMFilter and the obtained signal is not good I think because my desired sample frequency is too high (96KHz) and the libPDMFilter implements a big decimation and filtering oriented to lower frequencies (derived of a higher I2S freq, I know), so I would want to try with another approach than yours FIR based, but I dont know how set cutoff freq to obtain a good signal at 96 KHz. If you have any suggest in this terms I would be very grateful, thanks in advance.

alanbarr commented 6 years ago

Your cutoff choice should be about finding a balance between the following points:

Depending how tight your requirements are, you might be able to increase the number of taps to improve attenuation.

j054n commented 6 years ago

Hi again Mr. Barr and sorry again for the inconveniences, According you suggest I have adjusted VCO-PLL-I2S clock chain to obtain 3.072 MHz below limits of PDMmic (3x yours), and apply FIR decimation of 32 with 256 taps and cutoff=18KHz to obtain desired samples at 96 KHz. The filter coeffs was designed with your script and the output plot is: fir and testing with a 16KHz sine signal is very bad. Could you tell me if the calculations are correct or the possible cause of my error? Thanks in advance.

alanbarr commented 6 years ago

If I recall correctly, the non-optimised (-O0) version of my project was unable to keep up with the rate of sampling. When I enabled -O2 the program was capable of handling one batch of samples before the next arrived. I cannot remember how much CPU time it took, but I suspect since you are sampling at 3x the frequency there is a good chance you are exceeding your available time slot (assuming your algorithm is similar to mine).

Try and profile your algorithm and determine if the number of cycles it needs is greater than the available cycles between between samples needing processed. If you are over, try and: