Issue accessing AXI4Lite bus signals wrapped in a VHDL record

[yotarid]

Hello,

To achieve a better readability of my VHDL code, I wrapped the AXI4Lite bus signals in a axi4lite_bus_type VHDL record.

  type axi4lite_bus_type is record
    -- AXI input bus interface
    s_axi_aclk    : std_logic;
    s_axi_aresetn : std_logic;
    s_axi_awaddr  : std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    s_axi_awprot  : std_logic_vector(2 downto 0);
    s_axi_awvalid : std_logic;
    s_axi_wdata   : std_logic_vector(AXI_DATA_WIDTH - 1 downto 0);
    s_axi_wstrb   : std_logic_vector((AXI_DATA_WIDTH/8) - 1 downto 0);
    s_axi_wvalid  : std_logic;
    s_axi_bready  : std_logic;
    s_axi_araddr  : std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0);
    s_axi_arprot  : std_logic_vector(2 downto 0);
    s_axi_arvalid : std_logic;
    s_axi_rready  : std_logic;

    -- AXI output bus interface
    s_axi_awready : std_logic;
    s_axi_wready  : std_logic;
    s_axi_bresp   : std_logic_vector(1 downto 0);
    s_axi_bvalid  : std_logic;
    s_axi_arready : std_logic;
    s_axi_rdata   : std_logic_vector(AXI_DATA_WIDTH - 1 downto 0);
    s_axi_rresp   : std_logic_vector(1 downto 0);
    s_axi_rvalid  : std_logic;
  end record axi4lite_bus_type;

The AXI4Lite bus record type is used my entity as follows:

    axi4lite_bus_io : inout axi4lite_bus_type

In my cocotb simulation I create my AxiLiteMaster as follows:

axi4lite_master = AxiLiteMaster(
        AxiLiteBus.from_prefix(dut, "axi4lite_bus_io.s_axi"),
        dut.axi4lite_bus_io.s_axi_aclk,
        dut.axi4lite_bus_io.s_axi_aresetn,
        reset_active_level=False,
    )

However, the simulation fails. Could you tell me if creating a AxiLiteMaster is possible when AXI4Lite signals are wrapped in a VHDL record ?

I am using cocotbext-axi version 0.1.24 and cocotb version 1.8.1.

Thanks in advance, Younes

[yotarid]

Hi,

Already coming back to you. I figured out that passing dut.axi4lite_bus_io instead of just dut solves the issue. Seems like the VHDL record is interpreted as an entity, thus giving access to the signal inside the record.

The AxiLiteMaster definition now looks like this:

    axi4lite_master = AxiLiteMaster(
        AxiLiteBus.from_prefix(dut.axi4lite_bus_io, "s_axi"),
        dut.axi4lite_bus_io.s_axi_aclk,
        dut.axi4lite_bus_io.s_axi_aresetn,
        reset_active_level=False,
    )

I feel like this is not the standard way of using the AxiLiteMaster constructor, but for now it is doing the trick for me. But please still let me know if there is a better way to do it.

Cheers, Younes

[alexforencich]

That is basically the intended method. Except, I recommend removing the "saxi" prefix in your record. Or, at least remove the "s", since the whole point of the record is to be used on both ends of the connection. If you remove the prefix completely, then you can use from_entity instead of from_prefix.