issue with axil_master.read

[constant007]

using a simple axi-ram.v

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, FallingEdge, Timer
from cocotbext.axi import AxiBus, AxiMaster, AxiLiteBus, AxiLiteMaster, AxiRam

@cocotb.test()
async def test_axi_example(dut):
    cocotb.start_soon(Clock(dut.clk, 10, 'ns').start())
    dut.rst.value = 1
    await Timer(50, 'ns')
    dut.rst.value = 0

    axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axi"), dut.clk, dut.rst)

    print("TEST DATA0")
    write_addr = 0x100
    write_data = (0xDEADBEFF).to_bytes(4,'little')
    print(f"w1{write_data}")

    await axil_master.write(write_addr, write_data)

    #read_data = await axil_master.read(write_addr, 4)
    read_resp = await axil_master.read(write_addr, 4)
    read_data = read_resp.data

    assert read_data == write_data, f"Read data {read_data} does not match written data {write_data}"

    print("TEST DATA1")
    await axil_master.write(0x0, (0x55aa55aa).to_bytes(4,'little'))
    await axil_master.write(0x4, (0x12345678).to_bytes(4,'little'))

    #await Timer(50, 'ns')
    await RisingEdge(dut.clk)
    read_resp = await axil_master.read(0x0, 4)
    read_data = read_resp.data

    await Timer(50, 'ns')
    await RisingEdge(dut.clk)

    print(f"read data {read_data}")
    read_resp = await axil_master.read(0x4, 4)
    read_data = read_resp.data
    print(f"read data {read_data}")
    print(f"read data finished")

log, axil_master.read data not match with write data

TEST DATA0
w3735928575
w1b'\xff\xbe\xad\xde'
    50.00ns INFO     cocotb.axi_lite_ram.s_axi          Write start addr: 0x00000100 prot: 2 data: ff be ad de
    70.00ns INFO     cocotb.axi_lite_ram.s_axi          Write complete addr: 0x00000100 prot: 2 resp: 0 length: 4
    70.00ns INFO     cocotb.axi_lite_ram.s_axi          Read start addr: 0x00000100 prot: 2 length: 4
   100.00ns INFO     cocotb.axi_lite_ram.s_axi          Read complete addr: 0x00000100 prot: 2 resp: 0 data: ff be ad de
TEST DATA1
   100.00ns INFO     cocotb.axi_lite_ram.s_axi          Write start addr: 0x00000000 prot: 2 data: aa 55 aa 55
   100.00ns INFO     cocotb.axi_lite_ram.s_axi          Write complete addr: 0x00000000 prot: 2 resp: 0 length: 4
   100.00ns INFO     cocotb.axi_lite_ram.s_axi          Write start addr: 0x00000004 prot: 2 data: 78 56 34 12
   130.00ns INFO     cocotb.axi_lite_ram.s_axi          Write complete addr: 0x00000004 prot: 2 resp: 0 length: 4
   140.00ns INFO     cocotb.axi_lite_ram.s_axi          Read start addr: 0x00000000 prot: 2 length: 4
   140.00ns INFO     cocotb.axi_lite_ram.s_axi          Read complete addr: 0x00000000 prot: 2 resp: 0 data: ff be ad de
read data b'\xff\xbe\xad\xde'
   190.00ns INFO     cocotb.axi_lite_ram.s_axi          Read start addr: 0x00000004 prot: 2 length: 4
   190.00ns INFO     cocotb.axi_lite_ram.s_axi          Read complete addr: 0x00000004 prot: 2 resp: 0 data: aa 55 aa 55
read data b'\xaaU\xaaU'
read data finished

[alexforencich]

need a waveform dump file and the HDL

[constant007]

in the wave , there are only 2 read op found, and addr & data right; but mismatch with the log

module axi_lite_ram(
    input wire clk,
    input wire rst,

    // AXI4 Master Write Address Channel
    input wire [31:0] s_axi_awaddr,
    input wire [2:0] s_axi_awprot,
    input wire s_axi_awvalid,
    output wire s_axi_awready,

    // AXI4 Master Write Data Channel
    input wire [31:0] s_axi_wdata,
    input wire [3:0] s_axi_wstrb,
    input wire s_axi_wvalid,
    output wire s_axi_wready,

    // AXI4 Master Write Response Channel
    output wire [1:0] s_axi_bresp,
    output wire s_axi_bvalid,
    input wire s_axi_bready,

    // AXI4 Master Read Address Channel
    input wire [31:0] s_axi_araddr,
    input wire [2:0] s_axi_arprot,
    input wire s_axi_arvalid,
    output wire s_axi_arready,

    // AXI4 Master Read Data Channel
    output wire [31:0] s_axi_rdata,
    output wire [1:0] s_axi_rresp,
    output wire s_axi_rvalid,
    input wire s_axi_rready
);

    // 内部寄存器用于存储数据
    reg [31:0] memory [0:1023];

    // 写地址通道处理
    reg write_addr_ready;
    assign s_axi_awready = write_addr_ready;

    // 写数据通道处理
    reg write_data_ready;
    assign s_axi_wready = write_data_ready;

    // 写响应通道处理
    reg write_resp_valid;
    assign s_axi_bvalid = write_resp_valid;
    assign s_axi_bresp = 2'b00; // OKAY响应

    // 读地址通道处理
    reg read_addr_ready;
    assign s_axi_arready = read_addr_ready;

    // 读数据通道处理
    reg [31:0] read_data;
    reg read_data_valid;
    assign s_axi_rdata = read_data;
    assign s_axi_rvalid = read_data_valid;
    assign s_axi_rresp = 2'b00; // OKAY响应

    // 写操作逻辑
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            write_addr_ready <= 0;
            write_data_ready <= 0;
            write_resp_valid <= 0;
        end else begin
            // 写地址和数据同时有效时,写入memory
            if (s_axi_awvalid && s_axi_wvalid) begin
                memory[s_axi_awaddr[11:2]] <= s_axi_wdata;
                write_addr_ready <= 1;
                write_data_ready <= 1;
                write_resp_valid <= 1;
            end else begin
                write_addr_ready <= 0;
                write_data_ready <= 0;
                write_resp_valid <= 0;
            end
        end
    end

    // 读操作逻辑
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            read_addr_ready <= 0;
            read_data <= 0;
            read_data_valid <= 0;
        end else begin
            // 读地址有效时,从memory读取数据
            if (s_axi_arvalid) begin
                read_data <= memory[s_axi_araddr[11:2]];
                read_addr_ready <= 1;
                read_data_valid <= 1;
            end else begin
                read_addr_ready <= 0;
                read_data_valid <= 0;
            end
        end
    end

    // Dump waves
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1, axi_lite_ram);
  end

endmodule

[alexforencich]

Your RAM is not implementing AXI correctly.

[constant007]

Your RAM is not implementing AXI correctly.

thanks, fixed it.