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alexforencich / cocotbext-eth

Ethernet interface modules for Cocotb
MIT License
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Generate Verilog design files from .py file #3

Open dipal004 opened 2 years ago

dipal004 commented 2 years ago

Hi, I am trying to generate the verilog files for the ethernet module from the .py files. I have used the pyverilog though it is giving some errors.

$ ~/Downloads/Pyverilog/eth$ python3 eth_mac.py Traceback (most recent call last): File "eth_mac.py", line 44, in from .version import version ImportError: attempted relative import with no known parent package

Can you please advise me how I can generate the synthesized verilog design files or are the verilog design files available already? Thank you

alexforencich commented 2 years ago

These are simulation models only, they are not intended to be converted to HDL. If you are looking for synthesizable verilog for Ethernet MACs, see https://github.com/alexforencich/verilog-ethernet , which contains synthesizable verilog code for a 10/100/1G MAC and a 10G/25G MAC.