alexforencich
commented
1 year ago Nice work, I'll work on getting that cleaned up.
The BARs have to be configured after creating the IP core instance. In the Corundum testbenches, it is usually done like so:
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)This will configure one or two BARs on function 0. If you want to configure BARs on all of the functions, then perhaps that should be wrapped in a loop or similar.
shroud404
I found some problems when I wanted to use it to simulate PCIE models with multi-PF. There is a problem when scanning for devices and functions in pci.py. First, in line 145, it should be
dev.pcie_id = PcieId(self.bus_num, d, f)instead ofdev.pcie_id = PcieId(self.bus_num, d, 0). Second, in line 152, the dev.header_type has changed inawit dev.setupfromvaltoval & 0x7f. So the judgment condition of if should beif dev.multifunction == 0:. Also, there is a mistake in device.py line 93:f.multifunction_devlce = Trueshould bef.multifunction_device = True. Last, I want to know how to set/change an EP's BAR count/BAR size. After I fixed the above issue, I set up anUltraScalePlusPcieDeviceto have two PFs. Like this:RC successfully enumerates two PFs, Device tree is: [00-01]---01.0-[01]-+-00.0/-00.1 Scanned to the BAR of PF0: pci 01:00.0: Mem BAR0 (64-bit) raw: 0xffffffffff00000c, mask: 0x0000000000ffffff, size: 16777216. But the BAR of PF1 is completely empty, I printed the register read: Config type 0 read, reg 0x004 print current dev 01:00.1 BAR 0 register is 00 Why PF0 with a right BAR set, and PF1 with no bar set?