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alexforencich / verilog-axi

Verilog AXI components for FPGA implementation
MIT License
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question: how to read this syntax? #35

Closed hughperkins closed 2 years ago

hughperkins commented 2 years ago

Hi, this isnt an issue, it's a question, about verilog, since you're using a notation I haven't seen before, and not quite sure how to Google.

At e.g. https://github.com/alexforencich/verilog-axi/blob/25912d48fec2abbf3565bbefe402c1cff99fe470/rtl/axi_fifo_wr.v#L183

reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;

So, I'm interpreting this to mean that, you create an 8 bit register m_axi_awlen_reg, and assign it the value of m_axi_awlen_next. However, I'm not sure what the 8'd0, does? I'm guessing it does something like assert the number of bits in m_axi_awlen_next? (I looked through verilog-std-1364-2005.pdf, eg section 6.2, 9.2, but wasn't able to find the relevant syntax).

alexforencich commented 2 years ago

Declare 8 bit reg m_axi_awlen_reg, initialize it to zero, declare 8 bit reg m_axi_awlen_next, initialize it to X.

hughperkins commented 2 years ago

Oh.... thanks! I assumed it was a declaration of a single register, but I see now that it declares two. Got it. thanks! :)