axil_ram. How to adjust rvaild delay.

alexforencich / verilog-axi

Verilog AXI components for FPGA implementation

MIT License

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axil_ram. How to adjust rvaild delay. #36

Closed cjhonlyone closed 2 years ago

cjhonlyone commented 2 years ago

I want to modify axil_ram.v to control block ram. But it is about two or three clock to read data from block ram. How can I modify to fit this feature?