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alexforencich / verilog-axi

Verilog AXI components for FPGA implementation
MIT License
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add option for initialization file for RAM #42

Open bunnie opened 1 year ago

bunnie commented 1 year ago

This commit adds a parameter MEM_INIT so you can pass a non-zero set of values to pre-populate a RAM's content.

This wouldn't be valid behavior for a silicon tape-out, but at least for Xilinx FPGAs this is supported.