alexforencich / verilog-axi

Verilog AXI components for FPGA implementation
MIT License
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WIP: Verilator Compatibility #47

Open benreynwar opened 1 year ago

benreynwar commented 1 year ago

These were the changes I needed to make to get test_axil_crossbar.py working with verilator, along with using cocotb-bus=0.1.1. If you think it would be useful, I can try to get all the tests passing in verilator with similar changes. If you'd rather not apply these changes to the repo, I'll just apply them locally to the modules that I'm using.