axi_interconnect Synthesis

[GGbang2]

Hello, I found that the "priority_encoder" was optimized out when synthesizing "axi_interconnect" using Vivado. Do you know the reason behind this? The following image shows the synthesis schematic results:

[alexforencich]

The Vivado optimizer can do strange things occasionally. It is a purely combinatorial block, perhaps the LUTs that make up the priority encoder got merged with other LUTs, so there is no longer a defined hierarchy. I think the hierarchy is a bit loose anyway, I have seen all sorts of odd stuff get pushed across hierarchy boundaries during optimization, resulting in some confusion while trying to track down timing failures and what not.