Q: is there any component for read data out of standard ram/fifo and then transfer the data to axi master

[constant007]

Q: is there any component for read data out of standard ram/fifo and then transfer the data to axi master

[alexforencich]

Does the AXI DMA module not do what you want?

[constant007]

Does the AXI DMA module not do what you want?

there is a module produce some data which is written into legacy dual port ram(or fifo); and then transfer this data using axi master; i review the code of dma, the data path is from axis then to axi amster; the source data interface is different

[alexforencich]

Well, a FIFO would be AXI stream or could be easily adapted to AXI stream. But, what about the CDMA module, plus the AXI RAM IF module?

[constant007]

Well, a FIFO would be AXI stream or could be easily adapted to AXI stream. But, what about the CDMA module, plus the AXI RAM IF module?

could axi_ram_rd_if & axi_cdma works together ? so the data-path ram_rd_resp_data->s_axi_rdata(axi_ram_rd_if )-> m_axi_wdata(cdma)