Open RiceShelley opened 4 months ago
in axi_crossbar.v
module axi_crossbar # ( ... // Master interface AW channel register type (output) // 0 to bypass, 1 for simple buffer, 2 for skid buffer parameter M_AW_REG_TYPE = {M_COUNT{2'd1}}, // Master interface W channel register type (output) // 0 to bypass, 1 for simple buffer, 2 for skid buffer parameter M_W_REG_TYPE = {M_COUNT{2'd2}}, // Master interface B channel register type (input) // 0 to bypass, 1 for simple buffer, 2 for skid buffer parameter M_B_REG_TYPE = {M_COUNT{2'd0}}, // Master interface AR channel register type (output) // 0 to bypass, 1 for simple buffer, 2 for skid buffer parameter M_AR_REG_TYPE = {M_COUNT{2'd1}}, // Master interface R channel register type (input) // 0 to bypass, 1 for simple buffer, 2 for skid buffer parameter M_R_REG_TYPE = {M_COUNT{2'd0}} )
M_X_REG_TYPE parameters in axi_crossbar are not passed onto the axi_crossbar_wr and axi_crossbar_rd instantiations in the body of the module.
in axi_crossbar.v
M_X_REG_TYPE parameters in axi_crossbar are not passed onto the axi_crossbar_wr and axi_crossbar_rd instantiations in the body of the module.