questions about about the AXI_DMA module

[Taohua-digital]

Hi,I have some problems about the AXI_DMA module,what does parameter OFFSET_WIDTH,OFFSET_MASK,ADDR_MASK and CYCLE_COUNT_WIDTH mean?Can I ask you for a AXI_DMA_RD_TB.V and AXI_DMA_WR_TB.V file？Maybe can help me understand this module,thanks.

[alexforencich]

OFFSET_WIDTH and OFFSET_MASK are part of the support for unaligned operations. Transfers through the DMA core need to be shifted by some offset between 0 and the number of bytes in the bus - 1 (AXI_STRB_WIDTH-1), and OFFSET_WIDTH is the width of this field in bits, the clog2 of the number of byte in the bus (AXI_STRB_WIDTH). OFFSET_MASK is then computed from this to mask off the LSBs of the address that correspond to the shift offset. In this case (addr & OFFSET_MASK) provides the shift offset. Similarly, ADDR_MASK selects the MSBs that correspond to the word address. In this case (addr & ADDR_MASK) provides the word address. CYCLE_COUNT_WIDTH determines the size of the cycle counters, which track the number of transfer cycles in each operation. The maximum number of cycles is (2**LEN_WIDTH)/AXI_STRB_WIDTH, so CYCLE_COUNT_WIDTH is the clog2 of that value.

The Verilog _tb files are all simple wrappers around the corresponding module so that it can be run as a cosimulation with MyHDL; the main testbench logic is in the python files.

[Taohua-digital]

Thanks.When i run the .py file,it shows that it can't find the MyHDL file. Additionally,i also have some problems with the definition of some registers,such as axis_cmd_last_cycle_offset_next/reg,axis_cmd_input_cycle_count_next/reg,axis_cmd_output_cycle_count_next/reg,i want to know what does these registers function as.

[alexforencich]

Yeah, you'll need to install myhdl, icarus verilog, and build and install myhdl.vpi so that icarus verilog can find it.

axis_cmd_last_cycle_offset_next/reg is the number of bytes transferred on the AXI stream interface in the last cycle, axis_cmd_input_cycle_count_next/reg is the number of transfer cycles on the input side, and axis_cmd_output_cycle_count_next/reg is the number of transfer cycles on the output side. The cycle count on the AXI side may be 1 larger than the AXI stream side, depending on the alignment and length, so there may be one additional cycle required to transfer data in than to transfer data out or vise-versa.

[Taohua-digital]

Thanks for your answer.I am trying to follow your suggestion to build and install myhdl.vpi.

[Taohua-digital]

Hi,do you have the documents of the definition of these registers in axi_dma_rd.v/axi_dma_wr.v code or some other documentions about your code?If so,I wonder if I'll have a chance to refer to it.I have learned about AXI for few days and it is a little bit difficult for me to understand.However,your coding helped me a lot and I really appreciate you.

[alexforencich]

I don't have any documentation, sorry. I may put together some documentation for the module interfaces and such, but most likely not for the module internals.

[alexforencich]

Instructions for building myhdl.vpi: https://github.com/myhdl/myhdl/blob/master/cosimulation/icarus/README.txt

[Taohua-digital]

OK,really thanks for your helping.

[Taohua-digital]

Hi,there is no response when i make the Makefile in ..../master/cosimulation/icarus using cygwin.I am wondering what is the problems with this.

[Taohua-digital]

Hi,I finally understand this code,thanks very much.And I would like to ask about axis_cmd_valid_reg/next and axis_cmd_ready these two registers, I am not sure whether I understand correctly.