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alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
710 stars 220 forks source link

Python version < 3.3 compatibility #1

Closed caryan closed 9 years ago

caryan commented 9 years ago
caryan commented 9 years ago

Closing this PR to make a new PR off a branch so I can make more changes to my forked master.