Width mismatch in axis_arb_mux

[olofk]

I fixed all the Verilator warnings in https://github.com/alexforencich/verilog-axis/pull/9 except for one. For this one I have three functionally equivalent solutions but they all introduce various levels of ugliness so I would like to have your input on which one to choose. Let me know which you prefer and I'll swing you another patch

Option 1

diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index 72a3de5..130430b 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -66,7 +66,7 @@ module axis_arb_mux #
     input  wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
     input  wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
     input  wire [S_COUNT-1:0]            s_axis_tvalid,
-    output wire [S_COUNT-1:0]            s_axis_tready,
+    output reg [S_COUNT-1:0]            s_axis_tready,
     input  wire [S_COUNT-1:0]            s_axis_tlast,
     input  wire [S_COUNT*ID_WIDTH-1:0]   s_axis_tid,
     input  wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
@@ -104,7 +104,10 @@ reg  [DEST_WIDTH-1:0] m_axis_tdest_int;
 reg  [USER_WIDTH-1:0] m_axis_tuser_int;
 wire                  m_axis_tready_int_early;

-assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
+always @* begin
+   s_axis_tready = {S_COUNT{1'b0}};
+   s_axis_tready[grant_encoded] = (m_axis_tready_int_reg && grant_valid);
+end

Option 2

diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index 72a3de5..ea00ea9 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -104,7 +104,9 @@ reg  [DEST_WIDTH-1:0] m_axis_tdest_int;
 reg  [USER_WIDTH-1:0] m_axis_tuser_int;
 wire                  m_axis_tready_int_early;

+/* verilator lint_off WIDTH */
 assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
+/* verilator lint_on WIDTH */

 // mux for incoming packet
 wire [DATA_WIDTH-1:0] current_s_tdata  = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];

Option 3

index 72a3de5..cbbe1ad 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -104,7 +104,7 @@ reg  [DEST_WIDTH-1:0] m_axis_tdest_int;
 reg  [USER_WIDTH-1:0] m_axis_tuser_int;
 wire                  m_axis_tready_int_early;

-assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
+assign s_axis_tready = {{S_COUNT-1{1'b0}},(m_axis_tready_int_reg && grant_valid)} << grant_encoded;

 // mux for incoming packet
 wire [DATA_WIDTH-1:0] current_s_tdata  = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];