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alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
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Endianness of axis_fifo_adapter #12

Closed pfrankis closed 4 years ago

pfrankis commented 4 years ago

I'm using the axis_fifo_adapter with an input data width of 32 and output data width of 8. I was surprised to see that the output data stream seems to come out in little endian. For example if the input data word is "DEAD_BEEF", it's coming out of the FIFO as "EF", "BE", "AD", "DE".

Is this by design? I would have expected the fifo to use Netowrk byte order or have an option to do that. Am I doing something wrong?

alexforencich commented 4 years ago

This is how ordering in AXI stream works. For a byte-oriented stream, tdata[7:0] is the first byte, tdata[15:8] is the second, etc. So if you convert from 32 bits to 8 bits, tdata[7:0] comes out first, then tdata[15:8], then tdata[23:16], then tdata[31:24], then tdata[7:0] of the next input word, etc. See the AXI stream spec for more information - ARM IHI 0051A section 2.3.1. How those bytes are interpreted in terms of most/least significant (endianness) is out of scope. If you want to send the MSB first, then you need to byte-reverse the data before sending it over AXI stream. There is no option to change that because it would break basically all of the AXI stream components that expect the first byte in tdata[7:0].

pfrankis commented 4 years ago

Thank you so much for taking the time to explain. This makes sense