search

alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
710 stars 220 forks source link

Python File simulation idea how to import packages #13

Open BansariK opened 4 years ago

BansariK commented 4 years ago

python some module file giving module error how to solve it??? alleast give some file related info in each file

alexforencich commented 4 years ago

What are you doing, and what error are you getting?

BansariK commented 4 years ago

when I try to install any package like myhdl so but test_axi.py ..I run so full output I can't see in command prompt i want create log file for simulation results but for that python logging package its giving error. how to resolve it? ex : pip install logging

Regards Bansari Kansagara +91 9924098474

On Mon, 23 Mar 2020 at 10:36, Alex Forencich notifications@github.com wrote:

What are you doing, and what error are you getting?

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/alexforencich/verilog-axis/issues/13#issuecomment-602387723, or unsubscribe https://github.com/notifications/unsubscribe-auth/AMVV5JBEGVXYF36FRVPYTZLRI3U35ANCNFSM4LRSZFEA .

BansariK commented 4 years ago

Hello Alex,

can you help out regarding the specification that you have verified AXI? I want to register specifications. please help me out of my requirements.

Regards Bansari Kansagara +91 9924098474

On Mon, 23 Mar 2020 at 10:49, Bansari Kansagara bansari.kansagara@gmail.com wrote:

when I try to install any package like myhdl so but test_axi.py ..I run so full output I can't see in command prompt i want create log file for simulation results but for that python logging package its giving error. how to resolve it? ex : pip install logging

Regards Bansari Kansagara +91 9924098474

On Mon, 23 Mar 2020 at 10:36, Alex Forencich notifications@github.com wrote:

What are you doing, and what error are you getting?

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/alexforencich/verilog-axis/issues/13#issuecomment-602387723, or unsubscribe https://github.com/notifications/unsubscribe-auth/AMVV5JBEGVXYF36FRVPYTZLRI3U35ANCNFSM4LRSZFEA .

alexforencich commented 4 years ago

Without telling me what the errors are, I can't help you. What do you mean, register specifications?

BansariK commented 4 years ago

axil_register.v /axi_register.v file in rtl so regard that any clear specification or whole project specification you got with rtl.

Regards Bansari Kansagara +91 9924098474

On Mon, 23 Mar 2020 at 12:08, Alex Forencich notifications@github.com wrote:

Without telling me what the errors are, I can't help you. What do you mean, register specifications?

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/alexforencich/verilog-axis/issues/13#issuecomment-602413278, or unsubscribe https://github.com/notifications/unsubscribe-auth/AMVV5JAJX7J4ITV2KXHLVD3RI37VTANCNFSM4LRSZFEA .