edge case bug in axis_frame_len.v

alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation

MIT License

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edge case bug in axis_frame_len.v #16

Closed guruofquality closed 2 years ago

guruofquality commented 3 years ago

If there is a barrage of back to back single transfer packets (with last set on every transfer) the internal frame length counter doesn't clear. So instead the output frame length for each packet continues to grow in size, accumulating larger with each single transfer packet.

alexforencich commented 3 years ago

I think I have it fixed; let me know if you're still running in to an issue with that.