Intel quartus axis_async_fifo constraints

[alexisfrjp]

Quartus gives HOLD slack using the quartus and quartus_pro constraint files.

• rd_ptr_gray_reg[1] rd_ptr_gray_sync1_reg[1]
• rd_ptr_gray_reg[0] rd_ptr_gray_sync1_reg[0]
• rd_ptr_gray_reg[2] rd_ptr_gray_sync1_reg[2]
• wr_ptr_update_sync3_reg wr_ptr_update_ack_sync1_reg

The problem is the Data Required Path, clock path:

[alexforencich]

Unfortunately, the only solution I have found for this is to use clock groups. Which is a terrible solution because clock groups are terrible and should never be used, ever. But unfortunately timing constraint support in Quartus is also terrible, so I have not been able to find a better solution for setting a "datapath only" delay constraint that supersedes all other setup and hold constraints.

[alexforencich]

If you have a better idea though, please let me know!