alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
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Async FIFO does not reset #2

Closed caryan closed 9 years ago

caryan commented 9 years ago

Steps to reproduce:

1) Push data into a dual clock FIFO with back pressure applied by holding output_axis_tready low. 2) Reset the FIFO. 3) Release the FIFO reset and the data will then come out.

Expected behaviour: resetting will empty the FIFO.

alexforencich commented 9 years ago

Fixed, and added tests