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alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
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axis_adapter lost data #24

Closed captainliuy closed 1 year ago

captainliuy commented 1 year ago
  1. use TKEEP and TLAST signal;
  2. Slave width is 250 bytes;
  3. Master width is 4 bytes;

250 = 62 * 4 + 2, then the last 2 bytes lost

alexforencich commented 1 year ago

Looks like I don't have any checks to make sure things divide evenly. In this case, it should stop synthesis due to the configuration being unsupported.

captainliuy commented 1 year ago

Looks like I don't have any checks to make sure things divide evenly. In this case, it should stop synthesis due to the configuration being unsupported.

  1. change Slave width to 252 bytes;
  2. s_axis_tdata = {16'h0, tdata[250*8-1:0]};
  3. s_axis_tkeep = {2'h0, tkeep[250-1:0]}; It works!