alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
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axis_frame_length_adjust_fifo incorrect works with small header fifo length #30

Open derfe4 opened 7 months ago

derfe4 commented 7 months ago

Hi. I'm trying to use axis_frame_length_adjust_fifo in such a way that length_max* HEADER_FIFO_DEPTH<< FRAME_FIFO_DEPTH. In this situation, the fifo with headers is filled first. The input AXI interface of the axis_frame_length_adjust module looks fine. But the AXI output interface continues to keep a high level of the m_axis_valid signal at the end of the transaction. Thus, the data FIFO is filled with invalid data and when reading a data packet, its length does not correspond to the length that got into the fifo of the headers. 298112602-c4d63623-1455-4948-88ea-bd311139e213