Requesting elaboration on axis_adapter

[keegandent]

So firstly, thank you for these modules, they've been super useful to me as somebody still new to RTL design.

I just want to confirm my findings on the axis_adapter. I hooked it up to your great axis_uart module and found that when I send [b'\xbf', b'\x80'] in that order over UART, the Xilinx ILA shows the output of the axis_adapter as b'\x80\xbf'. It seems to me that the axis_adapter is expecting things in little-endian byte/word order, but the bytes/words themselves are big-endian. Is this part of the AXI4 standard or can I submit a PR to make a flag parameter that changes the word order?

Additionally, is this accomplished by simply replace indexing instances of seg_reg with (SEG_COUNT - seg_reg - 1)?

[alexforencich]

This has been asked before. The ordering is specified in the AXI stream spec, section 2.3.1: "In a data stream the low order bytes of the data bus are the earlier bytes in the stream." So if whatever you're connecting wants the bytes in a different order, it is not compliant with the AXI stream specification.

[keegandent]

Thanks for the quick response. In that particular case, I guess I will need to define a byte-order swapping module in hardware, because UART is a byte big-endian protocol I think

[alexforencich]

UART is little-endian at the bit level (LSB is sent first). I don't think there is a specification for the byte ordering, that's going to be up to the higher-level protocol.

[alexforencich]

Also, what do you mean by

the Xilinx ILA shows the output of the axis_adapter as b'\x80\xbf'

? It should be giving you the result in hex like 0x80bf, no?

[keegandent]

Also, what do you mean by

the Xilinx ILA shows the output of the axis_adapter as b'\x80\xbf'

? It should be giving you the result in hex like 0x80bf, no?

I was just expressing it in the same python bytestring format, but yes the format you mentioned is what shows up in the Vivado Hardware Manager’s waveform GUI. Thanks for your patience explaining this. I’ll just have to make a simple byte-swap module to sit between this and my core.

[alexforencich]

In [1]: (0x80bf).to_bytes(2, 'little')
Out[1]: b'\xbf\x80'

In [2]: (0x80bf).to_bytes(2, 'big')
Out[2]: b'\x80\xbf'

If you send b'\xbf\x80', in little endian that's 0x80bf.