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alexforencich / verilog-axis

Verilog AXI stream components for FPGA implementation
MIT License
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Some questions about axis_async_fifo #8

Closed Zeks-lzhang closed 4 years ago

Zeks-lzhang commented 4 years ago

Dear alexforencich, when using axis_async_fifo.v in this repository, I met some questions and I'm not sure whether it's just designed for this, so I want to seek for help for these quesions: 1.if I just write data in this fifo, and don't read→ that means m_axis_tready keep deasserted, in this situation, store_output will assert , and fifo is not empty, so it will perform read, and rd_ptr_reg will continually plus 1 until empty is asserted , but in fact I am not ready to read, these data will be ignored.

  1. In this fifo's read logic, it seems that tvalid's asserting depends on whether tready is asserted or not, but axi4s protocol said that 'it's not permitted to wait until TREADY is asserted before asserting TVALID'. Hoping for you advice for these questions,thanks!
alexforencich commented 4 years ago

  1. this is fine, the FIFO has two output pipeline registers to improve timing. This usually gets merged into the block RAM by the tools. The read pointer will increment until this pipeline is full. No data will be dropped if m_axis_tready is low.

  2. m_axis_tvalid is directly driven by a register, so there is no combinatorial path. Also, m_axis_tvalid is set regardless of the state of m_axis_tready (specifically, the condition is m_axis_tready || !m_axis_tvalid ). Obviously there has to be some dependence so that m_axis_tvalid can be de-asserted when m_axis_tready is high when the FIFO empties.

Zeks-lzhang commented 4 years ago

Now I know that , Sincere thanks to your answer!