Open maxscheel opened 2 years ago
Unfortunately, if the PHY is wired to MIO, it's hard to access from the FPGA side. I have not looked in to what it would take to make something like that work - it may be possible, and it may require running some code on the ARM to forward the MIO connections somehow, or it simply might not be possible for something reasonably fast like RGMII. But with a Zynq, I think it's basically expected that you're going to run petalinux or similar, and use the Ethernet port on the ARM side for SSH or whatever. If you're not using the ARM cores for your project, then I think you're probably going to have better luck with a non-Zynq board since you'll have direct access to everything.
Hi! I am currently looking into cost effective solutions for transforming multiple input bit streams (datarate of 244bit8MHz ~768 MBit/s) into UDP packages to send to a PC for storage/post-processing.
I stumbled across this project which looks amazing! I was hoping to be able to port the Digilent Nexys Video example to the much smaller Digilent Cora Z7-07S (xc7z007sclg400-1).
The Cora Z7 07S uses a Realtek RTL8211E-VL (MIO Bank 501 (1.8V) RGMII for data and MDIO for management). Given the hybrid ARM architecture of the zynq7000 I am sceptical, whether a port of the example project can be done easily.
Can I use a Zynq, or am I better of with something like a Nexys Video Artix-7?
Cheers