alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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ICMP echo #114

Open proconsule opened 2 years ago

proconsule commented 2 years ago

Hi, thanks for this great project. I tried the UDP/IP stack with an ARRIA 10 SX (TERASIC HAN PILOT board) using quartus 21.1. All works good (UDP echo on port 1234 works very well and arp also) i know that icmp isn't supported, so i am trying to make it work (have ping makes connectivity test very easy) i used udp_complete_64 as starting point (since i am using a 10g fiber) but i cant figure out the packet flow.

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have you any suggestion of a way to implement it in the right way (inside the ip_complete_64 module maybe?) or is the way i used the right way?

thanks

fpgapsyc commented 2 years ago

You can implement it on the IP layer. I have done the same and is working fine and tested on the board

proconsule commented 2 years ago

You can implement it on the IP layer. I have done the same and is working fine and tested on the board

Can you share the code?

EdwinEstep commented 6 months ago

You can implement it on the IP layer. I have done the same and is working fine and tested on the board

I'm also curious. Could you add it to your public fork of verilog-ethernet?