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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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Timing problem on GoWin GW1NR-LV9QN88PC6/I5 - Tang Nano 9k #118

Closed lk-davidegironi closed 1 year ago

lk-davidegironi commented 2 years ago

I'm trying to port your project to the GoWin FPGA GW1NR-LV9QN88PC6/I5, which is available on the cheap Tang Nano 9k development board. I'm using RTL8211E as PHY, connected with RGMII. I've run you project on Xilinx Zynq-7 without problem. On this GoWin I've problem, I suppose related to the timing (I'm not an FPGA expert).

I'm sending this test UDP packet

0000   02 00 00 00 00 00 6c 5a b0 f9 95 49 08 00 45 00
0010   00 42 00 00 00 00 ff 11 25 d9 c0 a8 0a 01 c0 a8
0020   0a 80 04 d2 04 d2 00 2e 82 3e 77 77 77 77 77 77
0030   77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77
0040   77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77

But looking at the Gowin Analyzer Oscilloscope (something like ILA on Vivado), it seems I receive the wrong data (see fpga_core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tdata[7:0])

Capture_1

Another things that make me think about time error is the Timing Analysis Report, Max freq for the RX clock is 85Mhz almost instead of 125Mhz, also the main clock is slowed down.

Capture_2

Capture_3

Main PLL generate 125Mhz (124.875Mhz) and 90 phas 125Mhz clock that are feeded in the fpga_core module.

And I've those 3 warnings during the synth phase: _WARN (TA1117) : Can't calculate clocks' relationship between: "RGMII_rx_clk" and "Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk" WARN (TA1117) : Can't calculate clocks' relationship between: "Gowin_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk" and "RGMII_rx_clk" WARN (PR1014) : Generic routing resource will be used to clock signal 'RGMII_rx_clkd' by the specified constraint. And then it may lead to the excessive delay or skew

Reading issues https://github.com/alexforencich/verilog-ethernet/issues/47 and https://github.com/alexforencich/verilog-ethernet/issues/46 I've implemented my own iddr and oddr, also on axis_gmii_rx and axis_gmii_tx I'm using the custom lsfr module https://github.com/alexforencich/verilog-ethernet/blob/47ca9a8725dba00990341470b6af37148c50c5ec/rtl/eth_crc_8.v

Any suggestion?

Find full project code (if someone want to take a look on it) attached.

nettest.zip

alexforencich commented 2 years ago

If it doesn't close timing, it's not gonna work correctly. If Fmax is reported as 85 MHz, there is no way it will work at the 125 MHz that's required by a gigabit Ethernet connection. Seems like that's just a super slow FPGA, so maybe running at 100 Mbps instead of 1 Gbps would make sense as that only requires 25 MHz.

lk-davidegironi commented 2 years ago

Thanks Alex, that makes sense. I'm trying the GoWIN cause they perform synth + place & route very fast. As reference, same project on my i7 Vivado 2021.2 for Zynq 7 takes 7 min, GoWIN takes 30 seconds. I've RTL8211E as PHY, connected with RGMII. Is there a way to run thus at 100Mbps?

lk-davidegironi commented 1 year ago

Solved, I don't use anymore the RTL8211E