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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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NetFPGA_SUME for kintex ultrascale #177

Open SrodinW opened 10 months ago

SrodinW commented 10 months ago

Hi. I succses used this project with a little bit modifications for 10G ethernet kintex7. Now I want to apply ip ten_gig_pcs_pma_0.xci for ultrascale. The specification PG068 states that I should use txusrclk_out2 like clock for send udp data. But when i connect clk156 = txusrclk_out2, then link down and txusrclk_out2 = 0. And when i use coreclk as the 156clk then udp packet drop on server. May be, do you now smth about this problem?

alexforencich commented 10 months ago

Why not start with an example design for Kintex Ultrascale, such as the ExaNIC X10? (or the X25 for UltraScale+)

SrodinW commented 10 months ago

I got the right clock frequency txusrclk_out2 for mac and data. and i can send to host PS, but i have broblems with pcs layer(local fault) and my host had fdir_miss and rx_packet_errors on udp. i just started working with fpga and some things don't understand. why in project ExaNIC X10 for kintex ultrascale don't use ip for pcs\pma(10g ethernet pcs\pma) or it's include in ip gtwizard? when i generate ip gtwizard, i don't uderstand when i should use full or only channel.. and if i use 10g-base-r data 64 bit, then gtrefclk should be156.25(asynchr 64/66b), right? it isn't depend on gth or gty i use?