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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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Fix padding on the 32-bit axis xgmii converter #183

Closed victorrjimenezz closed 10 months ago

victorrjimenezz commented 11 months ago

frame_min_count_reg was not being updated on the 32 bit axis xgmii converter. Thus padding was not working. Updated the reg on clk to have it work.

alexforencich commented 10 months ago

Good catch. It doesn't need a reset though, as it's reset at the top of the idle state, which is the state it's in when coming out of reset.

alexforencich commented 10 months ago

I went ahead and fixed this in the repo without the extra reset. Let me know if you find any other problems.

victorrjimenezz commented 10 months ago

Awesome! I will let you know if I find any other bugs 👍